Compulsory exercise

This is an individual assignment. You are of course allowed to discuss the problems, but you have to submit individually. The deadline is April 16.

Remember to state the reasoning behind the choices you make when answering these questions.

Part I: Problem 10.10 from the textbook.

Part II: Charge pump PLL design

1. Assume that you have a high quality (low phase noise) reference clock available, and that area is a concern. Do you choose Q = 0.1 or Q = 0.5?
2. Choose a reasonable loop bandwidth for an input reference frequency of 16 MHz.
3. Determine the component values for R, C1, and C2 in figure 19.7, assuming the desired output frequency is 320 MHz, Kosc = 2pi 10^7 rad/V/s, and Ich = 40 uA.
4. If you are to implement the PLL in the TSMC 90 nm LP process, what is the required area of the passive components? Relate this area to an approximation of the gate area required for the charge pump control logic.

Good luck, and ask questions if you need help.