Beskjeder

Preliminary organization of the lab groups: see FYS4220 home page.

The exam this year may be written, and not oral as in previous years. The reasons for this are: 1) many students and 2) problem solving in programmable logic / VHDL design may not be so easy to "carry out on the fly" during an oral examination. However, since the course description defines an oral exam, all students who have confirmed to follow the course must agree to a change. An email will be sent from the administration to the students.

Following students have registered for FYS4220, but have not yet confirmed by email to Bernhard: Alya Ali Hossain, Fan Zhang.

Deadline for confirmation to attend the course is Monday 30.8, either by attending the lecture that day or by email to Bernhard! This is necessary for organizing the lab! Those who have already signed up for the VHDL/FPGA lab do not need to take any further action.

Please send an email to <t.b.skaali@fys.uio.no> such that you can receive messages. FYS 4220 home page

The VHDL part of the course will be given by Jan Kenneth Bekkeng <j.k.bekkeng@fys.uio.no>, based on the book <Digital system design with VHDL, second edition, by Mark Zwolinski>. The lectures given by Skaali and Bekkeng are available as lecture notes from the FYS4220 home page. Our email addresses are <t.b.skaali@fys.uio.no> (phone 9520 9239) and <jan-kenneth.bekkeng@ffi.no>.