Semesterside for FYS4220 - Høst 2014
Faglærere
-
Ketil Røed Universitetet i Oslo
Lecture plans
Lectures
- 1 Introduction FPGA
- 2 Introduction VHDL
- 3 VHDL process
- 4 State machines
- 5a Package & subprograms
- 5b Intro testbenk
- 5c Variables vs signals
- 6 Test bench
- 7 Intro. Embedded system and NIOS II
- 8 NIOS II development
- 9 Intro. RTOS
- 10 Intertask communication I
- 11 Intertask communication II
- 12 Intertask communication III
- 13 Summary
- Metastability ans synchronization
Lab. assignments
- Lab 1 - Assignment
- Lab 2 - Introduction
- Lab 2 - Assignment
- Lab 3 - Introduction
- Lab 3 - Assignment
- Lab3.zip