HW Design videos

Digital HW design Q&A 1

Sequential circuit design

Outline

• Introduction (zip-file)
• Asynchronous reset (zip-file)
• Gated clocks (zip-file)
• Derived clocks (zip-file)
• Binary/Gray counters (zip-file)
• Ring counters (zip-file)
• LFSR (zip-file)
• PWM (zip-file)
• Register file (zip-file)
• FIFO (zip-file)
• VHDL Arrays (zip-file)

Register Transfer MethodoIogy I

Outline (zip-file)

• Introduction to Register Transfer Methodology (zip-file)
• FSMD overview (zip-file)

Digital HW design Q&A 2

Register Transfer MethodoIogy II

Outline

• FSMD Performance (zip-file)
• Example: One-shot-pulse-generator (zip-file)
• Example: GCD (Greatest Common Divisor) circuit (zip-file)
• Repetitive addition multiplier  (zip-file) (NOTE: This is from chapter 11.6 and is NOT syllabus).
• Repetitive addition multiplier (alternate design)  (zip-file) (NOTE: This is from chapter 11.6 and is NOT syllabus).
• Repetitive addition multiplier (add and shift)  (zip-file) (NOTE: This is from chapter 11.6 and is NOT syllabus).

Clock domain crossings and handshake

Outline

• Handshake (zip-file)
• CDC (Clock Domain Crossing) (zip-file)

All videos above can be downloaded from this zip-file